Digital circuits, such as those used in microprocessor units (MPUs), digital signal processors (DSPs), dynamic random access memory (DRAMs), programmable memory (e.g., EPROMs, EEPROMs, and flash), and application specific integrated circuits (ASICs), are characterized by signal propagation durations which become shorter with each decrease in switching element size and with corresponding increases in switching element integration density. These shorter signal propagation times can be exploited by reducing a clock cycle's period (i.e., increasing clock signal frequency) to perform logical functions more rapidly.
However, signal propagation time in integrated digital circuits is finite and non-uniform due to the parasitic capacitance, inductance, and resistance of interconnections and process variation of circuit elements. The non-uniformity of signal propagation has increased with integration density and circuit complexity such that signal propagation times cannot be reliably predicted.
Consider, for example, a circuit in which related signals are propagated in parallel such as respective bits of a binary code. If a logical combination of the bits is to be reliably performed, it is imperative that the bits be present and determinable of the intended logic state when the logical combination is to be performed. Traditional approaches include waiting until all signals are unconditionally settled at their desired logic state or inserting latches to store logic states at appropriate locations in the propagation path. Either solution undesirably reduces the operational speed of the logic function. Accordingly, it has become common practice to insert adjustable delay elements in select signal paths in order to synchronize the arrival of related signals at a desired location within a circuit.
In general, it is also common practice to generate delays in digital signals by propagating signals through a chain of serially connected inverter circuits. While some variation in propagation time is inevitable, the propagation time through a pair of inverters is a sufficiently small time increment to approximate a required delay. However, since propagation time may vary between stages and collectively over multiple stages (e.g. due to temperature, supply voltage, manufacturing process variations and other operational and environment conditions), it is desirable to provide the ability to program (i.e., adjust) a delay element to reduce the design burden of designing particular delay elements to achieve specified signal delay times. Thus, adjustable delay elements are used in integrated circuits as a viable mechanism for adjusting signal timing.
FIG. 1 schematically shows a typical prior art circuit 100 including an adjustable delay element 120. The adjustable delay element 120 receives a signal to be delayed along connection 115, labeled “IN,” and generates a delayed representation of the received signal on connection 125, labeled “OUT.” The adjustable delay element 120 includes a network of circuit elements 125 characterized by a total resistance, Rtot, between an input and an output of the adjustable delay element 125 and a total capacitance, Ctot, coupled in parallel with the output. The adjustable delay element 120 operates in accordance with a control bus 102, labeled “PVT[n,0],” that is tasked to controllably increase or decrease one or both of Rtot and Ctot. The network of circuit elements 125 generates a time constant, τ, equal to the product of the total resistance along and the total capacitance parallel to the internal connection. The time constant is increased by controllably increasing one or both of the resistance (Rtot) and the capacitance (Ctot) in the network of circuit elements 125.
FIG. 2 includes a graphical representation of output signal voltage (i.e., a signal on connection 125 of the prior art circuit 100 of FIG. 1. FIG. 2 represents time in picoseconds along the horizontal axis and normalized electrical potential in volts along the vertical axis. As shown in FIG. 2, a digitally programmable prior art circuit 100 responsive to a three bit control word can adjust the time it takes the normalized voltage to achieve a corresponding percentage of a steady-state voltage. For example, trace 201 is a time-varying voltage that achieves 90% of its normalized steady-state voltage in approximately 23 picoseconds (ps). As shown in the key to the right of the graph, the trace 201 includes points depicted with a plus sign (+). The control point that resulted in the trace 201 is characterized by a control word of 000. In contrast, trace 202 achieves 90% of its normalized steady-state voltage in approximately 45 ps. The trace 202 includes points depicted with an x. The control point responsible for the trace 202 is characterized by a control word of 001. Time-varying signal traces 203 through 208 include points depicted with respective unique symbols. Each of the signal traces 203 through 208 is characterized by a respective control word that directs the prior art circuit 100 to apply an increasing resistance or capacitance. Accordingly, each of the signal traces 203 through 208 achieves 90% of its normalized steady-state voltage in respective longer times with trace 205 through 208 unable to achieve the 90% level within 100 ps.
An inherent requirement of all reactive networks, including RC network based delay elements, is that the signal node needs to fully charge and discharge for predictable and repeatable signal behavior. Generally, it takes one time constant or 1τ, where τ=R×C, for an RC network to achieve about 63% of its steady-state voltage and about 5τ for the RC network to achieve its steady-state voltage. Consequently, a prior art circuit 100 that uses an RC network based delay element will only properly function when the desired delay is a small fraction of the period of the desired switching rate. As shown in FIG. 2, increasing the delay (i.e., increasing the time constant of the RC network) causes the output voltage to not fully charge within the given time of 100 ps. As a result, subsequent signal transitions occur before the RC network is capable of achieving a steady-state voltage. Consequently, prior art delay elements based on a reactive network develop a frequency induced delay variation for clock periods or data transactions that are shorter than approximately 5τ. This frequency dependency causes logical signal switching times to be dependent on operating frequency.